Search - vhdl uart

[VHDL-FPGA-Verilog] UART(FPGA)

Description: 基于现场可编程逻辑器件（FPGA）使用VHDL语言QuartusII实现UART通讯-Based on field programmable logic device (FPGA) using VHDL language QuartusII achieve UART communications
Platform: | Size: 14336 | Author: 刘磊 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于FPGA的多调制UART的设计，相当不错，可估参考-FPGA-based multi-modem UART design, very good reference to assess
Platform: | Size: 1124352 | Author: 吴宏伟 | Hits:

[ARM-PowerPC-ColdFire-MIPS] uart

Description: 用ALTERA的芯片做的多串口代码，内部做了3个通用串口，适合51 ARM等CPU，有完整的ALTERA工程和仿真波形-uart FOR ALTERA
Platform: | Size: 1571840 | Author: 郭强 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于vhdl的串口通信模块，即异步收发机，可实现单片机核fpga的收发串口通信，遵从rs232协议，已经调试过，很不错的资源-Vhdl-based serial communication module, that is, asynchronous transceiver can achieve single-chip transceiver nuclear fpga serial communication, rs232 to comply with the agreement, has been testing, it is a good resource
Platform: | Size: 1024 | Author: 郭帅 | Hits:

[Com Port] uart

Description: 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
Platform: | Size: 3072 | Author: 赵云 | Hits:

[Other] S7_PS2_RS232

Description: 利用cpld作为cpu控制器将ps2中取得按键值通过串口传送给pc机-cpld verilog ps2 UART
Platform: | Size: 1438720 | Author: wphyl | Hits:

[Com Port] uart16550

Description: uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
Platform: | Size: 1760256 | Author: CloudZhang | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
Platform: | Size: 25600 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart接口读写控制器，已经在fpga上测试通过-uart interface to read and write controller, has been tested by fpga
Platform: | Size: 3072 | Author: zhuq | Hits:

[File Format] uart

Description: 异步串行接口设计 vhdl设计 fpga下载模拟-this is a vhdl programm
Platform: | Size: 10240 | Author: jack | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart - veiloghdl rx, tx, baudrate-uart- veiloghdl rx, tx, baudrate
Platform: | Size: 5120 | Author: xinha | Hits:

[VHDL-FPGA-Verilog] UART-CPLD

Description: 使用VHDL在CPLD上设计UART的一个项目-VHDL design UART
Platform: | Size: 6302720 | Author: yuyue | Hits:

[VHDL-FPGA-Verilog] uart16550_latest[1].tar

Description: 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character length, parity, stop bits and baud rate generator.
Platform: | Size: 1559552 | Author: lisa1027 | Hits:

[Com Port] UART

Description: 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the procedures and instructions, validate through, with good stability and reference value!
Platform: | Size: 2269184 | Author: Kerwin | Hits:

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[VHDL-FPGA-Verilog] UART(FPGA)

[VHDL-FPGA-Verilog] uart

[ARM-PowerPC-ColdFire-MIPS] uart

[VHDL-FPGA-Verilog] uart

[Com Port] uart

[Other] S7_PS2_RS232

[Com Port] uart16550

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[File Format] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART-CPLD

[VHDL-FPGA-Verilog] uart16550_latest[1].tar

[Com Port] UART

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] fifouart_latest.tar

[VHDL-FPGA-Verilog] UART

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